This invention relates to a method for fabricating a semiconductor device having bipolar transistors and N and P channel MOS (CMOS) field effect transistors (FETs) on the same Si substrate.
A semiconductor device that has both bipolar transistors and CMOS transistors is generally called as a BiCMOS device.
A method for fabricating a BiCMOS device on a Si substrate is disclosed in, e.g., U.S. Pat. No. 4,503,603. This process is based on fabricating steps that use a first dielectric layer on the Si substrate that later serves as the gate oxide (insulator) of the finished FETs. The dielectric layer remains unchanged throughout the process in which it forms a part of a masking layer composed of the first dielectric layer, which is SiO.sub.2 and a second, nitride dielectric layer. The dielectric layers are formed on the substrate while defining on the substrate regions (wells) of a first conductivity type and a second conductivity type, which is the reverse of the first conductivity type, for fabricating the bipolar transistors and MOSFETs on the Si substrate.
Thus, this conventional process needs the following 8 mask steps:
A first mask step to define the regions (wells) of the second conductivity type on the substrate. A second mask step which makes the above-described first dielectric layer over the whole substrate except for the emitter and collector contact regions of the bipolar transistor, the gate region of the P channel MOSFET and source and drain regions adjacent to the gate and their contact regions to provide back bias to the substrate of PMOS FET and the NMOS FET regions. A third mask step to mask against ion implantation to form the base region of bipolar transistor, the source and drain of PMOS FET, and the contact regions on the substrate in the first conductivity. A fourth mask step to mask against the ion implantation to form the collector, emitter and contact regions of the substrate for the PMOS FET and the source and drain for the NMOS FET. A fifth mask step to provide ion implantation for the source and drain of NMOS FET, which are adjacent to its gate to form its channel region. A sixth and a seventh mask step to define the contact regions and their interconnection, and an eighth mask step to interconnect the contact regions after masking a passive, protective layer on the surface.
So, with the traditional method, there are:
(1) unstable threshold voltages caused by the non-uniform distribution of impurities after the successive etching and oxidation processes associated with the above mask steps, because the gate insulators of the CMOS FETs are covered by the second, nitride dielectric layer as a mask against the oxidation processes;
(2) disadvantages that the electrical characteristics of the CMOS FETs are controlled by the conditions of the bipolar transistor fabrication process; and
(3) many mask steps, which may even increase to 10 mask steps to provide the separate masking required if ion implantation is used to control the threshold voltage of the PMOS and NMOS FETs too.